1. Field of the Invention
The present invention relates generally to microelectronic packaging and, more particularly, to a method and apparatus for improving laminate performance in a ball grid array (BGA) package.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
The packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Several technologies have been developed to provide a means of mounting these electrical components on a surface of a substrate, such as a printed circuit board (PCB). Fine pitch surface mount (FPT), pin grid array (PGA), and ball grid array (BGA) are examples of leading surface mount technologies.
BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multi-layer interconnect options; higher IO""s for a given footprint; easier extension to multi-chip modules; and faster design-to-production cycle time. A BGA integrated circuit (I/C) package generally includes an I/C chip, such as a memory device, mounted on the top surface of a substrate. The I/C chip may be electrically coupled to the substrate by bond wires.
Regardless of the type of surface mount technology chosen, three common mounting techniques used to attach the I/C chip to the substrate include chip-on-board (COB), board-on-chip (BOC), and flip-chip (F/C). For COB packages, the I/C chip may be attached to the substrate xe2x80x9cface-upxe2x80x9d. That is to say that the side of I/C chip containing the bond pads for wire bonding the chip to the substrate is left exposed on the top surface. The backside of the I/C chip, which does not contain the bond pads, is adhered to the substrate. In this type of package, bond wires are attached to the exposed surface of the chip down to pads on the top surface of the substrate. The substrate contains electrical traces which route the signals from the top side of the substrate to external connections.
Alternately, the integrated circuit die may be mounted on the substrate xe2x80x9cface-down,xe2x80x9d as in a BOC package. In this instance, the substrate typically contains a slot. Since the I/C chip is mounted face-down, the bond pads on the surface of the chip are arranged to correlate with the slot opening in the substrate. Bond wires are attached from the bond pads on the chip, through the slot on the substrate, and to the backside of the substrate. The substrate contains electrical routing to distribute electrical signals along the backside of the substrate.
For F/C packages, the integrated circuit die is mounted on the substrate face-down as in the BOC package. However, in a F/C package bond wires are not used to electrically couple the I/C chip to the substrate. Instead, solder bumps located on the face of the chip are aligned with conductive pads on the mounting side of the substrate. The solder bumps may be re-flowed to electrically couple the chip to the substrate. The substrate contains electrical routing to distribute the electrical signals from the die along the backside of the substrate.
Regardless of the mounting techniques used to attach an I/C chip to a substrate, BGA substrates contain conductive routing which allows the signals to pass from the I/C chip to landpads on the backside of the substrate. A plurality of solder balls are deposited and electrically coupled to the landpads on the backside of the substrate to be used as input/output terminals for electrically connecting the substrate to a PCB or other external device.
The substrate is generally a laminate made up of many layers of thin material. Because the substrate is comprised of several layers of material which have been bonded together, the integrity between layers of material may provide a failure mechanism in the I/C package. Solder ball-to-landpad or landpad-to-substrate integrity, which may be critical to the functionality of the I/C package, are particularly susceptible to delamination due to mechanical stresses associated with handling and shipping of the I/C packages. This is especially true when the part is processed through electrical testing, since the packages are frequently being loaded and unloaded in and out of test sockets. Cratering, pad lifting, and ball shearing are typical failure modes which are associated with laminates.
The present invention may address one or more of the problems set forth above.
Certain aspects commensurate in scope with the disclosed embodiments are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In one embodiment of the present invention, there is provided a system comprising a processor and an integrated circuit package. The integrated circuit package is operatively coupled to the processor, the integrated circuit package comprising an integrated circuit die coupled to a substrate, the substrate comprising a first surface and a second surface, the second surface having a plurality of pads, each pad having one or more conductive traces extending on the second surface therefrom and configured to increase the shear strength of the pad as compared to the pad alone.
In another embodiment of the present invention, there is provided an integrated circuit package comprising an integrated circuit die and a substrate coupled to the integrated circuit die and comprising a first surface and a second surface, the second surface having a plurality of pads, each pad having one or more conductive traces on the second surface extending therefrom and configured to increase the shear strength of the pad as compared to the pad alone.
In yet another embodiment of the present invention, there is provided a substrate comprising a first surface and a second surface, the second surface having a plurality of pads, each pad having one or more conductive traces on the second surface extending therefrom and configured to increase the shear strength of the pad as compared to the pad alone.
In still another embodiment of the present invention, there is provided a method of building an integrated circuit package comprising the acts of: providing a substrate having a first surface and a second surface, the second surface having a plurality of pads, each pad having one or more conductive traces on the second surface extending therefrom and configured to increase the shear strength of the pad as compared to the pad alone; and disposing an integrated circuit die onto the substrate.
In still another embodiment of the present invention, there is provided a system comprising a processor and an integrated circuit package. The integrated circuit package is operatively coupled to the processor, the integrated circuit package comprising an integrated circuit die coupled to a substrate, each substrate comprising a first surface and a second surface, the second surface having an array of landpads, the array comprising four corner landpads, each of the four corner landpads having one or more conductive traces extending planarly therefrom and configured to increase the shear strength of the pad.
In still a further embodiment of the present invention, there is provided an integrated circuit package comprising an integrated circuit die and a substrate coupled to the integrated circuit die and comprising a first surface and a second surface, the second surface having an array of landpads, the array comprising four corner landpads, each of the four corner landpads having one or more conductive traces extending planarly therefrom and configured to increase the shear strength of the pad.
In yet a further embodiment of the present invention, there is provided a substrate comprising a first surface and a second surface, the second surface having an array of landpads, the array comprising four corner landpads, each of the four corner landpads having one or more conductive traces extending planarly therefrom and configured to increase the shear strength of the pad.
In yet another embodiment of the present invention, there is provided a substrate comprising a first surface and a second surface, the second surface having an array of landpads and four out-rigger pads, each of the out-rigger pads having one or more conductive traces extending planarly therefrom and configured to increase the shear strength of the pad.
In still a further embodiment of the present invention, there is provided a method of manufacturing an integrated circuit package comprising the acts of: manufacturing a plurality of BGA substrates comprising a plurality of landpads and a plurality of solderballs; testing the substrates for failure mechanisms associated with a dislodging of the solderballs; and; re-designing the substrates such that the landpads exhibiting the failure mechanisms are configured to increase the shear strength of the landpad.
In still another further embodiment of the present invention, there is provided a method of building an integrated circuit package comprising the acts of: providing a substrate comprising a first surface and a second surface, the second surface having an array of landpads, the array comprising four corner landpads, each of the four corner landpads having one or more conductive traces extending planarly therefrom and configured to increase the shear strength of the pad; and disposing an integrated circuit die onto the substrate.